Field
The disclosure relates to an integrated circuit package and method for fabricating a coreless substrate integrated circuit (IC) package with die side capacitors and a conductive layer.
Background
As electronic devices are getting smaller and faster, the demand for integrated circuit (IC) packages with higher I/O count, faster data processing rate, and better signal integrity greatly increases. Today packaging technologies such as wire bond lead-frame and conventional ball grid array (BGA) are not suitable for the high speed and data demands of ultra-thin and small electronic devices (e.g., smart watch, smart glasses, etc.).
The performance of integrated circuits in high performance electronic devices highly depends on the ICs' power delivery/distribution network (PDN). The impedance of the PDN can greatly affect the signal integrity (SI) of the overall IC. Specifically, the overall impedance from ground & power planes location, length of metal traces, number of vias and bumps, etc., can greatly impact the electrical performance.
The thickness (z-height) of an IC package can also affect the electrical performance of an IC. In particular, the thickness of an IC substrate is highly correlated with parasitic capacitance, inductance, and resistance, all of which affect the electrical performance of the system. Accordingly, what is needed is an improved IC package having a smaller z-height and an improved SI and PDN.